Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as, medical, automobile, and other applications. The technology used to manufacture image sensors, and in particular, CMOS image sensors (“CIS”), has continued to advance at great pace. For example, the demands of higher resolution and lower power consumption have encouraged the further miniaturization and integration of these image sensors. FIG. 1 illustrates a conventional CIS module 100. CIS module 100 operates by illuminating object 105 with light sources 110 (e.g., multicolor LEDs). The light reflected off object 105 is focused onto a CIS array 115, which includes a two dimensional array of optical sensors. Once the impinging image is captured, pixel array 115 outputs analog image data 120 to a digital processing unit 125. Digital processing unit 125 includes analog-to-digital (“ADC”) circuitry to convert analog image data 120 to digital image data 130. Finally, digital image data 130 may be subsequently stored, transmitted, or otherwise manipulated by software/firmware logic 135.
As the process technology for fabricating CIS array 115 continues to advance into sub 2.2 micron pixel designs, focusing light into the individual photodiodes of CIS array 115 and reducing crosstalk between the pixels has become increasingly difficult. This difficulty arises due to the relatively small open metal area above each photodiode in CIS array 115. Conventional techniques for increasing the sensitivity and reducing cross talk include shrinking the height of the back end metal stack (metal and dielectric layers) above the photodiode and/or incorporating an embedded microlens. The metal stack height, including the intermetal dielectric layers, is constrained by the capacitive coupling of consecutive metal layers. This coupling adversely affects circuit timing and gain. Therefore reducing the metal stack height to increase sensitivity can negatively affect many aspects of CIS performance. Using an embedded microlens, that is, a microlens below the traditional top microlens in the inter-metal dielectric layers, adds significant process complexity. For instance, the top microlens is formed of polyimides, which cannot withstand the typical processing temperatures used during the deposition of the metal stack layers and therefore cannot be used to fabricate embedded microlenses. In addition, alignment of an embedded microlens to the top microlens and to the surface of the photodiode is difficult and increases in difficulty as the photodiode apertures continue to decrease in sub 2.2 micron CIS technology.